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ltc4417 1 4417f typical a pplica t ion fea t ures descrip t ion prioritized powerpath? controller the lt c ? 4417 connects one of three valid power supplies to a common output based on priority. priority is defined by pin assignment, with v1 assigned the highest priority and v3 the lowest priority. a power supply is defined as valid when its voltage has been within its overvoltage (ov) and undervoltage ( uv) window continuously for at least 256ms. if the highest priority valid input falls out of the ov/uv window, the channel is immediately disconnected and the next highest priority valid input is connected to the common output. tw o or more ltc4417s can be cascaded to provide switchover between more than three inputs. the ltc4417 incorporates fast non-overlap switching circuitry to prevent both reverse and cross conduction while minimizing output droop. the gate driver includes a 6 v clamp to protect external mosfets. a controlled output ramp feature minimizes start-up inrush current. open drain valid outputs indicate the input supplies have been within their ov/uv window for 256ms. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath, thinsot and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. priority switching from 12v v1 to 14.8v v2 a pplica t ions n selects highest priority supply from three inputs n blocks reverse and cross conduction currents n wide operating voltage range: 2.5v to 36v n C42v protection against reverse battery connection n fast switchover minimizes output voltage droop n low 28a operating current n <1a current draw from supplies less than v out n 1.5% input overvoltage/undervoltage protection n adjustable overvoltage/undervoltage hysteresis n p-channel mosfet gate protection clamp n cascadable for additional input supplies n 24-lead narrow ssop and 4 mm 4 mm qfn packages n industrial handheld instruments n high availability systems n battery backup systems n servers and computer peripherals irf7324 irf7324 irf7324 vs1 v1 v out valid1 valid2 valid3 v1: 12v wall adapter 2a output v2: 14.8v li-ion main/swappable v3: 12v sla backup uv1 ov1 806k 1m 1m 1m 39.2k 60.4k v2 uv2 ov2 1.05m 31.6k 68.1k v3 en shdn hys cas uv3 ov3 4417 ta01a 698k 16.9k 49.9k g1 vs2 vs3 g2 gnd ltc4417 g3 v2 v1 v3 = 0v, i l = 2a c l = 120f 50ms/div 4417 ta01b 2v/div v out v1 uv fault 14.8v 12v 14.8v
ltc4417 2 4417f a bsolu t e maxi m u m r a t ings supply voltages v 1, v 2, v3 ............................................... C 42 v to 42 v v out , vs 1, vs 2, vs 3 .............................. C 0.3 v to 42 v voltage from v 1, v 2, v3 to v out ................. C84 v to 42 v voltage from vs 1, vs 2, vs 3 to g 1, g 2, g3 .................................................. C 0.3 v to 7. 5 v input voltages en, shdn .............................................. C 0.3 v to 42 v ov 1, ov 2, ov 3, uv 1, uv 2, uv 3 ............... C0. 3 v to 6v hys ......................................................... C 0.3 v to 1v input currents ov 1, ov 2, ov 3, uv 1, uv 2, uv 3, hys ............... C3 ma o utput voltages valid 1 , valid 2 , valid 3 ........................ C 0.3 v to 42 v cas .......................................................... C 0.3 v to 6v output currents valid 1 , valid 2 , valid 3 , cas ............................. 2 ma o perating ambient temperature range ltc 4417 c ................................................ 0 c to 70 c ltc 4417 i.............................................. C40 c to 85 c ltc 4417 h .......................................... C4 0 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature gn package ( soldering , 10 sec ) ........................ 30 0 c (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead narrow plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 en shdn hys uv1 ov1 uv2 ov2 uv3 ov3 valid1 valid2 valid3 v1 v2 v3 vs1 g1 vs2 g2 vs3 g3 v out cas gnd t jmax = 150c, ja = 85c/w, jc = 30c/w 24 23 22 21 20 19 7 8 9 25 uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 uv1 ov1 uv2 ov2 uv3 ov3 vs1 g1 vs2 g2 vs3 g3 hys shdn en v1 v2 v3 valid1 valid2 valid3 gnd cas v out t jmax = 150c, ja = 47c/w, jc = 4.5c/w exposed pad (pin 25) pcb gnd connection optional p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4417cgn#pbf ltc4417cgn#trpbf ltc4417gn 24-lead narrow plastic ssop 0c to 70c ltc4417ign#pbf ltc4417ign#trpbf ltc4417gn 24-lead narrow plastic ssop C40c to 85c ltc4417hgn#pbf ltc4417hgn#trpbf ltc4417gn 24-lead narrow plastic ssop C40c to 125c ltc4417cuf#pbf ltc4417cuf#trpbf 4417 24-lead (4mm 4mm) plastic qfn 0c to 70c ltc4417iuf#pbf ltc4417iuf#trpbf 4417 24-lead (4mm 4mm) plastic qfn C40c to 85c ltc4417huf#pbf ltc4417huf#trpbf 4417 24-lead (4mm 4mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4417 3 4417f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. for all tests, v1 = vs1, v2 = vs2, v3 = vs3. unless otherwise noted, v1 = v2 = v3 = v out = 12v, hys = gnd. symbol parameter conditions min typ max units start-up v1-v3,v out v1 to v3,v out operating supply range l 2.5 36 v i v1-v3,vout(en) total supply current with channels enabled v1 = 5v, v2 = 12v, v3 = 2.5v, v out = 4v, (notes 3, 4) l 28 78 a i v1-v3(en) total supply current with channels disabled v1 = 5v, v2 = 12v, v3 = 2.5v, v out = en = 0v, (notes 3, 4) l 31 93 a i v1-v3(shdn) total supply current when shutdown v 1 = 5v , v 2 = 12v , v 3 = 2.5v , v out = shdn = 0v, (notes 3, 4) l 15.4 84 a i vout v out supply current v1 = 5v, v2 = 12v, v3 = 2.5v, v out = 4v l 14 30 a i priority current from highest v1 to v3 priority input source (v1) v1 = 5v, v2 = 12v, v3 = 2.5v, v out = 4v v1 = 5v, v2 = 12v, v3 = 2.5v, v out = en = 0v l l 2.6 20 6 45 a a i highest current from highest v1 to v3 voltage input source v1 = 5v, v2 = 12v, v3 = 2.5v, v out = 4v, (note 3, 4) l 11 72 a v1 = 5v, v2 = 12v, v3 = 2.5v, v out = en = 0v, shdn = 0v, (note 3, 4) l 15 80 a i lower current from v1 to v3 input voltage sources lower than v out v1 = 5v, v2 = 12v, v3 = 2.5v, v out = 4v not highest valid priority C5 0.2 1 a gate control ?v g open (vs C vg) clamp voltage v out = 11v, g1 to g3 = open l 5.4 6.2 6.7 v ?v g(source) sourcing (vs C vg) clamp voltage v out = 11v, i = C10a l 5.8 6.6 7 v ?v g(sink) sinking (vs C vg) clamp voltage v out = 11v, i = 10a l 4.5 5.2 6 v ?v g(off) g1 to g3 off (vs C vg) threshold v1 = v2 = v3 = 2.8v, v out = 2.6v, g1 to g3 rising edge l 0.12 0.35 0.6 v ?v g(slew,on) g1 to g3 pull-down slew rate v out = 11v, c gate = 10nf (note 5) l 4 9 20 v/s ?v g(slew,off) g1 to g3 pull-up slew rate v out = 11v, c gate = 10nf (note 6) l 7.5 13 22 v/s i g(dn) g1 to g3 low pull-down current v out = 2.6v, v1 to v3 = 2.8v, (g1 to g3) = ?v g + 300mv 0.8 2 7 a r g(off) g1 to g3 off resistance v out = 4v, v1 to v3 = 5v, i g = C10ma l 9 16 26 v rev reverse voltage threshold measure (v1 to v3) C v out , v out falling l 30 120 200 mv t g(switchover) pin break-before-make time v out = 11v, c gate = 10nf, (note 7) l 0.7 2 3 s t pg(shdn) g1 to g3 turn-off delay from shdn v out = 11v, falling edge shdn to (g1 to g3) = (vs1 to vs3) C 3v, c gate = 10nf l 20 50 100 s t pg(en,off) g1 to g3 turn-off delay from en v out = 11v, falling en edge to (g1 to g3) = (vs1 to vs3) C 3v, c gate = 10nf l 0.3 0.7 1.4 s t pg(en,on) g1 to g3 turn-on delay from en v out = 11v, rising en edge to (g1 to g3) = (vs1 to vs3) C 3v, c gate = 10nf l 1 1.4 2 s
ltc4417 4 4417f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. note 3: each v1 to v3 supply current specification includes current into the corresponding vs1 to vs3 for the channel(s) being tested. note 4: specification represents the total diode-ored current of v1 to v3 input supplies, selecting the highest voltage as the input source. if two input supplies are similar in voltage and higher than the remaining input supply voltage, the current is split evenly between the two higher voltage supplies. current is split evenly if all supplies are equal. note 5: falling edge of g1 to g3 measured from 11v to 8v. note 6: rising edge of g1 to g3 measured from 7v to 11v. note 7: uv1 driven below v ov,uv(thr) . time is measured from respective rising edge g1 to g3 crossing (vs1 to vs3) C 3v to next valid priority falling edge g1 to g3 crossing (vs1 to vs3) C 3v. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. for all tests, v1 = vs1, v2 = vs2, v3 = vs3. unless otherwise noted, v1 = v2 = v3 = v out = 12v, hys = gnd. symbol parameter conditions min typ max units input/output pins v valid (ol) valid1 to valid3 output low voltage i = 1ma, (v1 to v3) = 2.5v, v out = 0v l 0.25 0.55 v t p valid(off) valid1 to valid3 delay off from ov/uv fault l 5 8 13 s v cas(oh) cas output high voltage i = C1a l 1.4 2 3 v v cas(ol) cas output low voltage i = 1ma l 0.2 0.4 v i cas cas pull-up current shdn = 0v, cas = 1v l C6 C20 C40 a t pcas(en) cas delay from v g(off) v out = 11v l 0.4 0.7 1.3 s v en(thr) en threshold voltage en rising l 0.6 1 1.4 v v shdn(thr) shdn threshold voltage shdn rising l 0.4 0.8 1.2 v v shdn_en(hys) shdn, en threshold hysteresis 100 mv i shdn_en shdn, en pull-up current shdn = en = 0v l C0.5 C2 C5 a i leak shdn, en, valid1 to valid3, cas leakage current shdn = en = ( valid1 to valid3) = 36v, cas = 5.5v l 1 a ov, uv protection circuitry v ov_uv(thr) ov1 to ov3, uv1 to uv3 comparator threshold v out = 11v, ov1 to ov3 rising, uv1 to uv3 falling l 0.985 1 1.015 v v ov_uv(hys) ov1 to ov3, uv1 to uv3 comparator hysteresis v out = 11v l 15 30 45 mv i uv_ov(leak) ov1 to ov3, uv1 to uv3 leakage current ov1 to ov3 = 1.015v, uv1 to uv3 = 0.985v l 20 na i ov_uv(min) minimum external hysteresis current i hys = C400na l 35 50 75 na i ov_uv(max) maximum external hysteresis current i hys = C4a l 420 520 620 na v hys hys voltage i hys = C4a l 470 495 520 mv t valid v1 to v3 validation time 100 256 412 ms
ltc4417 5 4417f typical p er f or m ance c harac t eris t ics v g vs temperature gate falling slew rate vs temperature gate rising slew rate vs temperature i g(dn) vs temperature switchover time vs temperature valid delay off time vs temperature total shutdown supply current vs supply voltage total enabled supply current vs supply voltage i v1-v3,vout(en) vs supply voltage supply voltage (v) 0 total enable supply current (a) 40 35 25 30 20 10 15 5 0 10 20 30 4417 g02 40 all supply, vs and v out pins connected together supply voltage (v) 0 total shutdown supply current (a) 25 20 10 15 5 0 10 20 30 4417 g01 40 all supply and vs pins connected together, v out = 0v temperature (c) ?50 ?v g (v) 6.40 6.35 6.25 6.30 6.20 6.10 6.15 6.05 6.00 0 50 ?25 25 100 4417 g04 125 75 temperature (c) ?50 i g(dn) (a) 3.0 2.5 1.5 2.0 1.0 0.5 0 0 50 ?25 25 100 4417 g07 125 75 temperature (c) ?50 t g(switchover) (s) 3.0 2.5 1.5 2.0 1.0 0.5 0 0 50 ?25 25 100 4417 g08 125 75 temperature (c) ?50 valid delay time (s) 8.5 8.4 8.2 8.3 8.1 7.9 8.0 7.8 7.7 0 50 ?25 25 100 4417 g09 125 75 temperature (c) ?50 gate falling slew rate (v/s) 16 14 10 12 8 4 6 2 0 0 50 ?25 25 100 4417 g05 125 75 v1 = 2.7v v1 = 5v v1 = 12v v1 = 36v c gate = 10nf v1 = v2 = v3 v1 = 24v temperature (c) ?50 gate rising slew rate (v/s) 16 12 4 8 0 0 50 ?25 25 100 4417 g06 125 75 v1 = 2.7v v1 = 5v v1 = 12v, 24v, 36v v1 = v2 = v3 c gate = 10nf v2 = vs2 voltage (v) 0 i v1-v3,vout(en) (a) 16 14 10 12 8 4 6 2 0 10 20 30 4417 g03 40 v1 = vs1 = 5v v2 = vs2 v3 = vs3 = 2.8v v out = 4.9v
ltc4417 6 4417f typical p er f or m ance c harac t eris t ics v out switching from higher to lower voltage v out switching from lower to higher voltage with slew rate control circuitry reverse voltage blocking v valid (ol) vs pull-up current v ov,uv vs temperature deglitched connection p in func t ions cas: cascade output. digital output used for cascad- ing multiple ltc4417s. connect cas to en of another ltc4417 to increase the number of multiplexed input supplies. cas is pulled up to the internal v ldo voltage by an internal 20 a current source to indicate when all inputs are invalid, the external p-channel mosfets are determined to be off, and en is above 1 v. cas also pulls high when shdn is driven below 1 v. cas is pulled low when any input supply is within the ov/uv window for at least 256 ms and both shdn and en are above 1 v. cas also pulls low when en is driven below 1 v. cas can be driven to 5.5 v independent of the input supply voltages. leave open if not used. en: channel enable input. en is a high voltage input that allows the user to quickly connect and disconnect chan- nels without resetting the ov/uv timers. when below 1v, all external back-to-back p-channel mosfets are driven off by pulling g1, g2 and g3 to their respective vs1, vs2 and vs3. when above 1 v, the highest valid priority chan- nel is connected to the output. en is pulled to the internal v ldo voltage with a 2 a current source and can be pulled up externally to a maximum voltage of 36 v. leave open when not used. exposed pad ( uf package only): exposed pad may be left open or connected to device ground. pull-up current (ma) 0 v valid (ol) (v) 0.5 0.4 0.2 0.3 0.1 0 0.5 1.0 1.5 4417 g10 2.0 temperature (c) ?50 v ov,uv (v) 1.04 1.03 1.01 1.02 1.00 0.98 0.99 0.97 0.96 0 50 ?25 25 100 4417 g11 125 75 v uv(rising) v ov(falling) v ov,uv(thr) v2 v1 c l = 122f i l = 1a ?40v pch fdd4685 100ms/div 4417 g12 2v/div v out v1 = ?20v v1 = 20v c l = 122f i l = 1a ?40v pch fdd4685 5s/div 4417 g15 v2, v out 10v/div v2 v1 c l = 122f i l = 1a ?40v pch fdd4685 100s/div 4417 g13 2v/div v out v2 2v/div v1 2v/div i vout 5a/div r s = 1.43k c s = 6.8nf c l = 100f i l = 1a ?40v pch fdd4685 20s/div 4417 g14 v out
ltc4417 7 4417f p in func t ions g1, g2, g3: p-channel mosfet gate drive outputs. g1, g2 and g3 are used to control external back-to-back p- channel mosfets. when driven low, g1, g2 and g3 are clamped 6 v below their corresponding vs1, vs2 and vs3. connect g1, g2 and g3 to external p-channel mosfet gate pins. see dual channel applications section for con- necting unused channels. gnd: device ground. hys : ov / uv comparator hysteresis input. connecting hys to ground sets a fixed 30 mv hysteresis for the ov and uv comparators. connecting a resistor, r hys , between hys and ground disables the internal 30 mv hysteresis and sets a 63mv/r hys hysteresis current which is sourced from each ov1, ov2 and ov3 and sunk into each uv1, uv2 and uv3 pin. connect to ground when not used. ov1, ov2, ov3: overvoltage comparator inputs. rising voltages above 1 v signal an over voltage event, invalidating the respective input supply channel. connect ov1, ov2 and ov3 to an external resistive divider from its respective v1, v2 and v3 to achieve the desired overvoltage threshold. the comparator hysteresis can be set to an internally fixed 30mv or set externally via the hys pin. connect unused pins to ground. shdn : shutdown input. driving shdn below 0.8 v turns off all external back-to-back p-channel mosfet devices, forces the ltc4417 into a low current state, and resets the 256 ms timers used to validate v1, v2 and v3. driving shdn above 0.8 v allows channels to validate and connect. shdn is pulled high to the internal v ldo voltage with a 2a current source and can be pulled up externally to a maximum voltage of 36v. leave open when not used. uv1, uv2, uv3: undervoltage comparator inputs. falling voltages below 1 v signal an undervoltage event, invalidat- ing the respective input supply channel. connect uv1, uv 2 and uv3 through a resistive divider between the respec- tive v1, v2 and v3 and ground to achieve the desired undervoltage threshold. the comparator hysteresis can be set to an internally fixed 30 mv or set externally via the hys pin. connect pins from unused channels to ground. v 1: highest priority input supply. when v 1 is within its user defined ov/uv window for 256 ms, it is connected to v out via its external back-to- back p- channel mosfets. connect v1 to ground when channel is not used. see applications information for bypass capacitor recommendations. v2: second priority input supply. when v2 is within its ov/uv window for 256 ms, it is connected to v out via its external back-to-back p-channel mosfets only if v1 does not meet its ov/uv requirements. connect to ground when channel is not used. see applications information for bypass capacitor recommendations. v 3: third priority input supply. when v 3 is within its ov/ uv window for 256 ms, it is connected to v out via its external back-to-back p-channel mosfets only if v1 and v2 do not meet their ov/uv requirements. connect to ground when channel is not used. see applications information for bypass capacitor recommendations. valid1, valid2, valid3: valid channel indicator outputs. valid1 , valid2 and valid3 are high voltage open drain outputs that pull low when the respective v1, v2 and v3 are within the ov/uv window for at least 256 ms and release when the respective v1, v2 and v3 are outside the ov/ uv window. connect a resistor between valid1 , valid2 and valid3 and a desired supply, up to a maximum of 36v, to provide the pull-up. leave open when not used. vs 1, vs 2, vs3: external p-channel mosfet common sour ce connection. vs1, vs2 and vs3 supply the higher voltage of v1, v2 and v3 or v out to the gate drivers. connect vs1, vs2 and vs3 to the respective common source connection of the back-to-back p-channel mos- fets. connect to ground when channel is not used. see applications information section for bypass capacitor recommendations. v out : output voltage supply and sense. v out is an output voltage sense pin used to prevent any input supply from connecting to the output if the output voltage is not at least 120 mv below the input supply voltage. during nor- mal operation, v out powers most of the internal circuitry when its voltage exceeds 2.4v . connect v out to the output. see applications information section for bypass capacitor recommendations.
ltc4417 8 4417f func t ional b lock diagra m + ? + ? ldo prioritizer highest valid priority vb ldo v out v out vb ldo shdn i shdn 2a shdn 1v d2 p1 v3v2v1 ldo shdn v ldo v best v3 v2 v1 p2 p3 p4 p5 2.4v prioritized nonoverlap control logic v bestgen + ? vs1 350mv 120mv gate driver rev v gs vs1 v ldo v ldo bandgap uvlo v1 v2 gnd m3 m2 d1 cas v ldo v ldo i cas 20a v3 + ? en hys en i en 2a 1v 0.24v 0.5v m4 d3 v ldo v ldo i lim 5a v ldo current sense/8 + ? v ldo 1v + ? v ldo i hys/8 uv 1v m1 v ldo ov v ldo hys + ? ota 30mv 256ms timer external hys hysteresis ch1 valid uv1 uv2 uv3 ov1 ov2 ov3 channel 1 valid1 valid2 valid3 + ? + channel 2 channel 3 + ? + ? vs1 vs2 vs3 dz1 6.2v g2 g3 4417 bd g1 + ?
ltc4417 9 4417f ti m ing diagra m t valid t p valid(off) t pg(en,off) t pg(en,on) t pg(shdn) 4417 td t g(switchover) g2 g1 uv2 uv1 en shdn valid2 valid1
ltc4417 10 4417f o pera t ion the functional block diagram displays the main functional blocks of this device. the ltc4417 connects one of three power supplies to a common output, v out , based on user defined priority. connection is made by enhancing external back-to-back p-channel mosfets. unlike a diode-or, which always passes the highest supply voltage to the output, the ltc4417 lets one use a lower voltage supply for primary power and a higher voltage supply as second- ary or backup power. during normal operation the ltc4417 continuously moni- tors v 1, v 2 and v 3 through its respective ov1, ov2 and ov3 and uv1, uv2 and uv3 pins using precision overvoltage and undervoltage comparators. the highest priority input supply whose voltage is within its respective ov/ uv window for at least 256 ms is considered valid and is connected to v out through external back-to-back p-channel mosfets. valid1 , valid2 and valid3 pull low to indicate when the v1, v2 and v3 input supplies are valid. hysteresis on the ov and uv threshold is adjustable. connecting a resistor, r hys , between hys and ground forces 63mv/r hys current to flow out of ov1, ov2 and ov3 and into uv1, uv2 and uv3 to create hysteresis when outside their respective ov/uv windows. connecting hys to ground sets the ov and uv comparator hysteresis to 30mv. see the application information for more details. during channel transitions, monitoring circuitry prevents cross conduction between input channels and reverse con- duction from v out using a break - before - make architecture . the vgs comparator monitors the disconnecting channel s gate pin voltage ( g1, g2 or g3). when the gate voltage is 350mv from its common source connection ( vs1, vs2 or vs3), the vgs comparator latches the output to indicate the channel is off and allows the next valid priority input supply to connect to v out , preventing cross conduction between channels. the latch is reset when the channel is turned on. to prevent reverse conduction from v out to v1, v2 and v3 during channel switchover, the rev comparator monitors the connecting input supply ( v1, v2 or v3) and output voltage ( v out ). the rev comparator delays the connection until the output voltage droops lower than the input voltage by the reverse current blocking threshold of 120 mv. the output of the rev comparator is latched, resetting when its respective channel is turned off. the ltc4417 gate driver pulls down on g1, g2 and g3 with a strong p-channel source follower and a 2a current source. when the clamp voltage is reached, the p-channel source follower is back biased, leaving the 2a current source to hold g1, g2 and g3 at the clamp voltage. to minimize inrush current at start-up, the gate driver soft-starts the first input supply to connect v out , at a rate of around 5 v/ms terminating when any channel disconnects or 32 ms has elapsed. once slew rate control has terminated, the gate driver quickly turns on and off external back-to-back p-channel mosfets as needed. a shdn low to high transition or v out drooping below 0.7v reactivates soft-start. when en is driven above 1 v the highest valid priority input supply is connected to v out . the high voltage en comparator disconnects all channels when en is driven below 1 v. the ltc4417 continues to monitor the ov and uv pins and reflects the current input supply status with valid1 , valid2 and valid3 . when four or more sup- plies need to be prioritized, connect the higher priority ltc4417s cas to the lower priority ltc4417s en. if v out is allowed to fall below 0.7 v, the next connecting input supply is soft-started. the high voltage shdn comparator forces the ltc4417 into a low current state when shdn is forced below 0.8 v. while in the low current state, all channels are disconnected, ov and uv comparators are disabled, and all 256 ms timers are reset. when shdn transitions from low to high, the first validated input to connect to v out is soft-started. tw o separate internal power rails ensure the ltc4417 is functional when one or more input supply is present and above 2.3 v. v bestgen generates a vb ldo rail from the highest v1, v2 and v3 and v out voltage. vb ldo powers the uvlo, bandgap, and v out comparator. the internal v ldo powers all other circuits from v out provided v out is greater than 2.4 v. if v out is less than 2.3 v, v ldo powers all other circuits from the highest priority supply available. if all sources are invalid or the ltc4417 is shut down, v ldo connects to vb ldo .
ltc4417 11 4417f a pplica t ions i n f or m a t ion i ntroduction the ltc4417 is an intelligent high voltage triple load switch which automatically connects one of three input supplies to a common output based on predefined pin priorities and validity. v1 is defined to be the highest priority and v3 the lowest priority, regardless of voltage. an input supply is defined valid when the voltage remains in the user defined overvoltage ( ov) and undervoltage ( uv) window for at least 256ms. if a connected input supply falls out of the user defined ov/uv window and remains outside the ov/uv window for at least 8 s, the channel is disconnected and the next highest valid priority is connected to the common output. if a lower priority input supply is connected to v out and a higher priority input supply becomes valid, the ltc4417 disconnects the lower priority supply and connects the higher priority input supply to v out . typical ltc4417 applications are systems where predict- able autonomous load control of multiple input supplies is desired. these supplies may not necessarily be different in voltage, nor must the highest voltage be the primary supply. a typical ltc4417 application circuit is shown in figure 1. external component selection is discussed in detail in the following sections. vs1 v1 v out 3.3v 4a valid1 valid2 valid3 12v wall adapter c in1 2200f 7.4v li-ion primary battery uv1 ov1 r3 806k r2 39.2k r1 60.4k r6 931k r5 63.4k r4 137k r9 931k r8 63.4k r7 137k r10 1m r11 1m r12 1m primary invalid secondary invalid adapter invalid v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 f01 g1 vs2 vs3 g2 c vs3 0.1f gnd ltc4417 g3 irf7324 m5 m6 irf7324 m3 m4 irf7324 m1 m2 c vs2 0.1f c vs1 0.1f c v1 0.1f c v2 0.1f c v3 0.1f + c l 100f v out + + 7.4v li-ion secondary battery + ltc3690 switching regulator figure 1. typical hand held computer application.
ltc4417 12 4417f i hys/8 uv1 v1 input supply ltc4417 v1 1v valid1 1v hys 4417 f03 i hys r hys 124k to 1.24m uv1 valid ov1 r1 r2 r3 r7 r6 uv1 gnd i hys/8 v ldo dual- resistive connection + ? ov1 valid m1 r p v out + ? 256ms timer r5 r4 ov1 uv1 t-resistive connection optional independent hysteresis r9 r10 r8 r11 ov1 ov uv r12 a pplica t ions i n f or m a t ion figure 2. ov and uv thresholds and hysteresis voltage d efining o perational r ange to guard against noise and transient voltage events during live insertion, the ltc4417 requires an input supply remain in the ov/uv window for at least 256 ms to be valid. the ov/uv window for each input supply is set by a resistive divider ( for example, r1, r2 and r3 for v1 input supply) connected from the input supply to gnd, as shown in figure 1. when setting the resistive divider values for the ov and uv input supply threshold, take into consideration the tolerance of the input supply , 1.5% error in the ov and uv comparators, tolerance of r1, r2 and r3, and the 20na maximum ov/uv pin leakage currents. in addition to tolerance considerations, hysteresis reduces the valid input supply operating range. input supplies will need to be within the reduced input supply operating range to validate. referring to figure 2, v1 supply voltage must be greater than uv hys to exit the uv fault. if an ov fault occurs, the v1 supply voltage must return to a voltage lower than the ov hys voltage to exit the ov fault. reduced operating window ov/uv window ov uv v1 4417 f02 uv1 fault ov1 fault v1 valid ov hys uv hys hysteresis for the ov and uv comparators are set via the hys pin. two options are available. connecting a resistor, r hys , between hys and gnd, as shown in figure 3, sets the hysteresis current i ov_uv(hys) that is sunk into uv1, uv2 and uv3 and sourced out of ov1, ov2 and ov3. the value of r hys is calculated with equation (1). choose r hys to limit the hysteresis current to between 50 na and 500na. r hys = 63mv i ovuv(hys) (1) where 50na i ovuv(hys) 500na figure 3. ltc4417 external hysteresis independent ov and uv hysteresis values are available by separating the single string resistive dividers r1, r2 and r3, shown in figure?3, into two resistive strings, r4- r5 and r6-r7. in such a configuration, the top resistor defines the amount of hysteresis and the bottom resistor defines the threshold. use equations (2) and (3) to cal- culate the values. r top = hyst i ovuv(hys) (2) where hyst is the desired hysteresis voltage at v1. r bottom = r top ov/ uv threshold ( ) C 1 (3) when large independent hysteresis voltages are required, a resistive t structure can be used to define hysteresis values, also shown in figure 3. after the desired ov and uv thresholds are set with resistors r8 through r10, r11 and r12 are calculated using: r11 = r8 ? ov hys C i ovuv(hys) ? (r9 + r10) ? ? ? ? i ovuv(hys) ? (r8 + r9 + r10) (4) r12 = (r8 + r9) ? uv hys C i ovuv(hys) ? r10 ? ? ? ? i ovuv(hys) ? (r8 + r9 + r10) (5) where ov hys , uv hys are the desired ov and uv hysteresis voltage magnitudes at v1 through v3, and i ovuv(hys) is the programmed hysteresis current.
ltc4417 13 4417f a pplica t ions i n f or m a t ion reduction of the valid operating range can be used to prevent disconnected high impedance input supplies from reconnecting. for example, if 3 series connected aa alkaline batteries with a total series resistance of 675m is used to source 500 ma, the voltage drop due to the se- ries resistance would be 337.5 mv. once the batteries are discharged and are disconnected due to a uv fault, the aa battery stack would recover the 337.5 mv drop across the internal series resistance. using the 30 mv fixed internal hysteresis allows only 81 mv of hysteresis at the input pin, possibly allowing the input supply to revalidate and reconnect. using external hysteresis, the hysteresis volt- age can be increased to 400 mv, reducing or eliminating the reconnection issue, as shown in figure 4. f il tering n oise on ov and uv p ins the ltc4417 provides an 8 s ov/uv fault filter time. if the 8 s filter time is not sufficient, add a filter capacitor between the ov or uv pin and gnd to extend the fault filter time and ride through transient events. a uv pin fault filter time extension capacitor, c uvf , is shown in figure 5. use equation (6) to select c uvf for the uv pin and equa- tion (7) to select c ovf for the ov pin. c uvf = t delay ? r1 + r2 + r3 r3 ? (r1 + r2) ? ln v i C v f 1v C v f ? ? ? ? ? ? (6) c ovf = t delay ? r1 + r2 + r3 r1 ? (r2 + r3) ? ln v i C v f 1v C v f ? ? ? ? ? ? (7) where the final input voltage v f and the initial voltage v i are the resistively divided down values of the input supply step, as shown in figure 6. connecting hys to gnd, as shown in figure 5, selects an internal 30mv fixed hysteresis, resulting in 3% of the input supply voltage. figure 6. fault filter time extension 4417 f05 without fault filter time extension 1v v ovuv(thr) v in(init) v in(final) t delay with fault filter time extension input supply step v i = v in(init) ? (r1 + r2) r1 + r2 + r3 v f = v in(final) ? (r1 + r2) r1 + r2 + r3 figure 4. setting a higher uv hysteresis to prevent unwanted reconnections v1 400mv hysteresis fully charged 3 aa battery valid uv range for 81mv hysteresis valid uv range for 400mv hysteresis v1 uv fault and disconnects 337.5mv recovery when load is disconnected 81mv hysteresis 2.7v uv threshold 4417 f06 c uvf uv1 v1 input supply ltc4417 v1 1v 1.03v valid1 hys 4417 f04 uv1 valid ov1 ov uv r1 r2m2 r3 gnd optional filter capacitor optional disconnect + ? ov1 valid m1 r p v out + ? 256ms timer 1v 0.97v figure 5. ltc4417 internal hysteresis with optional filter capacitor and manual disconnect mosfet extending the filter time delay will result in a slower response to fast uv and ov faults. extending the uv pin fault filter time delay will also add delay to the ov pin. if this is not desirable, separate the single resistive string into two resistive strings, as shown in figure 3. p riorit y r eassignment a connected input supply can be manually disconnected by artificially creating a uv fault. an example is shown in figure 5. when n-channel mosfet, m2, is turned on, the
ltc4417 14 4417f a pplica t ions i n f or m a t ion uv1 pin is pulled below 1 v. the ltc4417 then discon- nects v1 and connects the next highest valid priority to v out . when selecting the external n-channel mosfet, be sure to account for drain leakage current when setting uv and ov thresholds by adjusting the resistive divider to consume more current. s electing e xternal p-c hannel mosfets the ltc4417 drives external back- to- back p- channel mosfets to conduct or block load current between an input supply and load. when selecting external p-channel mosfets, the key parameters to consider are on- resistance (r ds(on) ), absolute maximum rated drain to source break- down voltage (bv dss(max) ), threshold voltage (v gs(th) ), power dissipation, and safe operating area (soa). to determine the required r ds(on) use equation (8), where v drop is the maximum desired voltage drop across the two series mosfets at full load current, i l(max) , for the application. external p-channel mosfet devices may be paralleled to further decrease resistance and decrease power dissipation of each paralleled mosfet. r ds(on) v drop 2 ? i l(max) (8) the clamped gate drive output is 4.5v ( minimum) from the common source connection. select logic level or lower threshold external mosfets to ensure adequate overdrive. for applications with input supplies lower than the clamp voltage, choose external mosfet with thresholds suf- ficiently lower than the input supply voltage to guarantee full enhancement. it is imperative that external p-channel mosfet devices never exceed their bv dss(max) rating in the application. select devices with bv dss(max) ratings higher than seen in the application. switching inductive supply inputs with low value input and/or output capacitances may require additional precautions; see transient supply protection section in this data sheet for more information. in normal operation, the external p-channel mosfet de- vices are either fully on, dissipating relatively low power, or off, dissipating no power. however, during slew-rate controlled start-up, significant power is dissipated in the external p- channel mosfets. the external p- channel mosfets dissipate the maximum amount of power during the initial slew-rate limited turn on, where the full input voltage is applied across the mosfet while it sources current. power dissipation immediately starts to decrease as the output voltage rises, decreasing the voltage drop across the mosfet s. a conservative approach for determining if a particular device is capable of supporting soft-start, is to ensure its maximum instantaneous power, at the start of the output slewing, is within the manufacturers soa curve. first determine the duration of soft-start using equation (9) and find the inrush current into the load capacitor using equation (10). t startup = v in 5 v/ ms [ ] (9) i maxcap = c l ? 5000[v/s] (10) using v in and i maxcap , the power dissipated by the external mosfets during start- up, p ss , is defined by equation?(11). if the ltc4417 soft-starts with a live i l , the extra load cur- rent needs to be added to i maxcap , and p ss is calculated by equation (12). p ss = v in ? i maxcap (11) p ss = v in ? (i maxcap + i l ) (12) check to ensure p ss with a t startup single pulse duration lies within the safe operating area ( soa) of the chosen mosfet. ensure the resistive dividers can sink the drain- source leakage current at the maximum operating tem- perature. refer to manufacturers data sheet for maximum drain to source leakage currents, i dss . a list of suggested p-channel mosfets is shown in table?1. use procedures outlined in this section and the soa curves in the chosen mosfet manufacturers data sheet to verify suitability for the application.
ltc4417 15 4417f a pplica t ions i n f or m a t ion table 1. list of suggested p-channel mosfets v 1, v 2, v3 mosfet v th( max) v gs( max) v ds( max) max rated r ds( on) at 25c 5v si4465ady C1v 8v C8v 9m at C4.5v 11m at C2.5v 10v si4931dy* C1v 8v C12v 18m at C4.5v 22m at C2.5v 18v fds8433a C1v 8v C20v 47m at C4.5v 70m at C2.5v 18v irf7324* C1v 12v C20v 18m at C4.5v 26m at C2.5v 28v si7135dp C3v 20v C30v 6.2m at C4.5v 28v fds6675bnz C3v 20v C30v 22m at C4.5v 28v ao4803a* C2.5v 20v C30v 46m at C4.5v 36v sud50p04 C2.5v 20v C40v 30m at C4.5v 36v fdd4685 C3v 20v C40v 35m at C4.5v 36v fds4685 C3v 20v C40v 35m at C4.5v 36v si4909dy* C2.5v 20v C40v 34m at C4.5v 36v si7489dp C3v 20v C100v 47m at C4.5v *denotes dual p-channel r everse v oltage p rotection the ltc4417 is designed to withstand reverse voltages applied to v1, v2 and v3 with respect to v out of up to C84v. the large reverse voltage rating protects 36 v input supplies and downstream devices connected to v out against high reverse voltage connections of C42 v ( absolute maximum) with margin. select back- to- back p- channel mosfets with bv dss( max) ratings capable of handling any anticipated reverse voltages between v out and v1, v2 or v3. ensure transient voltage suppressors ( tvs ) connected to reverse connection pro- tected inputs (v1, v2 and v3) are bidirectional and input capacitors are rated for the negative voltage. r everse c urrent b locking when switching channels from higher voltages to lower voltages, the rev comparator verifies the v out voltage is below the connecting channels voltage by 120 mv before the new channel is allowed to connect to v out . this ensures little to no reverse conduction occurs during switching. an example is shown in figure 7. v2 is initially connected to v out when a higher priority input supply, v1, is inserted. the ltc4417 validates v1 and disconnects v2, allowing v out to decay from 18 v to 11.88 v at a slew rate determined by the load current divided by the load capacitance. once v out falls to 11.88v, the ltc4417 connects v1 to v out . s electing v out c apacitance to ensure there is minimal droop at the output, select a low esr capacitor large enough to ride through the dead time between channel switchover. a low esr bulk capacitor will reduce ir drops to the output voltage while the load current is sourced from the capacitor. use equation (13) to calculate the load capacitor value that will ride through the ov/uv comparator delay, t p valid(off) , plus the break- before-make time, t g(switchover) . c l i l(max) ? t g(switchover) + t pvalid(off) ( ) v out _droop(max) (13) where i l(max) is the maximum load current drawn and v out_droop(max) is the maximum acceptable amount of voltage droop at the output. equation (13) assumes no inrush current limiting circuitry is required. if it is required, refer to figure 8 and use the following equation (14) for c l . () ++ c i? tt 0.79 ?r ?c v l l( ma x) g( swit c hover )p val id(o ff) ss out _ droop (m ax ) (14) figure 7. reverse current blocking v1 validates v2 disconnects v1 connects at v out = 11.88v 4417 f07 256ms v out v1 = 12v v rev = 120mv v out v2 = 18v v1 = 12v dv out dt = i l c l
ltc4417 16 4417f a pplica t ions i n f or m a t ion where r s and c s are component values shown in figure?8. the selection of r s and c l involves an iterative process. begin by assuming 0.79 ? r s ? c s = 10 s and choosing c l using equation (14). see the inrush current and input voltage droop section for more details regarding inrush current limiting circuitry, and for selecting r s . figure 8. slew rate limiting gate drive c in1 68f c s vs1 ltc4417 g1 v out v out 4417 f08 r s d s bat54 12v wall adapter v1 irf7324 m1 m2 + c l 47f + c vs1 channel disconnects or 32 ms has elapsed. once soft-start has terminated, the gate driver quickly turns on and off external back-to-back p-channel mosfets as needed. a shdn low to high transition or v out drooping below 0.7v reactivates soft-start. i nrush c urrent and i nput v ol tage d roop when switching control of v out from a lower voltage supply to a higher voltage supply, the higher voltage supply may experience significant voltage droop due to high inrush current during a fast connection to a lower voltage output bulk capacitor with low esr. this high inrush current may be sufficient to trigger an undesirable uv fault. to prevent a uv fault when connecting a higher voltage input to a lower voltage output, without adding any inrush current limiting, size the input bypass capacitor large enough to provide the required inrush current, as shown by equation (15). c v1 c l ? v1C v out(init) v1 droop C 1 ? ? ? ? ? ? (15) where v out(init) is the initial output voltage when being powered from a supply voltage less than v1, c v1 is the bypass capacitor connected to v1, c l is the output capaci- tor and v1 droop is the maximum allowed voltage droop on v1. make sure c v1 is a low esr capacitor to minimize the voltage step across the esr. in situations where input and output capacitances can- not be chosen to set the desired maximum input voltage droop, or the peak inrush current violates the maximum pulsed drain current (i dm ) of the external p-channel mos- fets, inrush current can be limited by slew rate limiting the output voltage. the gate driver can be configured to slew rate limit the output with a resistor, capacitor and schottky diode, as shown in figure 8. the series resistor r s and capacitor, c s , slew rate limit the output, while the schottky diode, d s , provides a fast turn off path when g1 is pulled to vs1. with a desired input voltage drop, v1 droop , and known supply resistance r src , the series resistance, r s , can be calculated with equation (16), where ?v g(sink) is the ltc 4417s sink clamp voltage, v gs is the external g a te d river when turning a channel on, the ltc4417 pulls the common gate connection ( g1, g2 and g3) down with a p-channel source follower and a 2 a current source. vs1, vs2 and vs3 voltages at or above 5 v will produce rising slew rates of 12v / s and falling slew rates of 4 v / s with 10nf between the vs and g pins. vs1, vs2 and vs3 voltages lower than 5v will result in lower slew rates, see typical curves for more detail. as g1, g2 and g3 approaches the 6.2 v clamp voltage, the source follower smoothly reduces its current while the 2 a hold current continues to pull g1, g2 and g3 to the final clamp voltage, back biasing the source follower. clamping the g1, g2 and g3 voltage prevents any overvoltage stress on the gate to source oxide of the external back-to-back p-channel mosfets. if leakage into g1, g2 and g3 exceeds the 2 a hold current, the g1, g2 and g3 voltage will rise above the clamp voltage, where the source follower enhances to sink the excess current. when turning a channel off, the gate driver pulls the com- mon gate to the common source with a switch having an on-resistance of 16, to effect a quick turn-off. to minimize inrush current at start-up, the gate driver soft- starts the gate drive of the first input to connect to v out . the gate pin is regulated to create a constant 5 v/ms rise rate on v out . slew rate control is terminated when any
ltc4417 17 4417f a pplica t ions i n f or m a t ion p-channels gate to source voltage when driving the load and inrush current, c s is the slew rate capacitor and c l is the v out hold up capacitance. the output load current i l is neglected for simplicity. choose c s to be at least ten times the external p-channel mosfets c rss(max) , and c vs to be ten times c s . r s v g(sink) C v gs ( ) ? c l ? r src c s ? v1 droop (16) use equation (17) to verify the inrush current limit is lower than the absolute maximum pulsed drain current, i dm . i inrush = v1 droop r src (17) if the external p- channel mosfet s reverse transfer capacitance, c rss , is used instead of c s , replace c s with c rss in equation (16), where c rss is taken at the minimum v ds voltage, and calculate for r s . depending on the size of c rss , r s may be large. care should be used to ensure gate leakages do not inadvertently turn off the channel over temperature. this is particularly true of built in zener gate- source protected devices. careful bench characterization is strongly recommended, as c rss is non-linear. the preceding analysis assumes a small input inductance between the input supply voltage and the drain of the ex- ternal p-channel mosfet. if the input inductance is large, choose c v1 to be much greater than c l and replace r src with the esr of c v1 . when slew rate limiting the output, ensure power dis- sipation does not exceed the manufacturers soa for the chosen external p-channel mosfet. refer to the selecting external p-channel mosfets section. t ransient s uppl y p rotection the ltc4417s abrupt switching due to ov or uv faults can create large transient overvoltage events with inductive input supplies, such as supplies connected by a long cable . at times the transient overvoltage condition can exceed twice the nominal voltage. such events can damage external devices and the ltc4417. it is imperative that external back-to-back p-channel mosfet devices do not exceed their single pulse avalanche energy specification ( eas) in unclamped inductive applications and input voltages to the ltc4417 never exceed the absolute maximum ratings. to minimize inductive voltage spikes, use wider and/or heavier trace plating. adding a snubber circuit will dampen input voltage spikes as discussed in linear application note 88, and a transient surge suppressor at the input will clamp the voltage. transient voltage suppressors ( tvs ) should be placed on any input supply pin, v1, v2 and v3, where input shorts, or reverse voltage connection can be made. if short-circuit of input sources powering v out are possible, transient voltage suppressors should also be placed on v out , as shown in figure 9. when selecting transient voltage suppressors, ensure the reverse standoff voltage (v r ) is equal to or greater than the application operating voltage, the peak pulse current (i pp ) is higher than the peak transient voltage divided by the source impedance, the maximum clamping voltage (v clamp ) at the rated i pp is less than the absolute maxi- mum ratings of the ltc4417 and bv dss of all the external back-to-back p-channel mosfets. in applications below 20 v, transient voltage suppressors may not be required if the voltage spikes are lower than the bv dss of the external p- channel mosfets and the ltc4417 figure 9. transient voltage suppression fdd4685 fdd4685 m1 m2 24v wall adapter vs1 g1 v out ltc4417 input parasitic inductance output parasitic inductance c v1 0.1f c sn r sn c out 10f c l 330f v out or 4417 f09 d2 smbj26a d1 smbj26ca or + snubber
ltc4417 18 4417f absolute maximum ratings. if the bv dss of the external p-channel mosfet is momentarily exceeded, ensure the avalanche energy absorbed by the mosfets do not exceed the single pulse avalanche energy specification ( eas). voltage spikes can be dampened further with a snubber. i nput s uppl y and v out s horts input shorts can cause high current slew rates. coupled with series parasitic inductances in the input and output paths, potentially destructive transients may appear at the input and output pins. if the short occurs on an input that is not powering v out , the impact to the system is benign. back- to- back p- channel mosfets with their common gates connected to their common sources naturally prevent any current flow regardless of the applied voltages on either side of the drain connections, as long as the bv dss is not exceeded. if the short occurs on an input that is powering v out , the issue is compounded by high conduction current and low impedance connection to the output via the back-to-back p-channel mosfets. once the ltc4417 blocks the high input short current, v1, v2 and v3 may experience large negative voltage spikes while the output may experience large positive voltage spikes. to prevent damage to the ltc4417 and associated de- vices in the event of an input or output short, it may be necessary to protect the input pins and output pins as shown in figure 9. protect the input pins, v1, v2 and v3, with either unidirectional or bidirectional tvs and v out with a unidirectional tvs . an input and output capacitor between 0.1 f and 10 f with intentional or parasitic series resistance will aid in dampening voltage spikes; see linear technology s application note 88 for general consideration. due to the low impedance connection from v1, v2 and v3 to v out , shorts to the output will result in an input supply uv fault. if the uv threshold is high enough and the short resistive enough, the ltc4417 will disconnect the input. the fast change in current may force the output below gnd, while the input will increase in voltage. if uv thresholds are set close to the minimum operating voltage of the ltc4417, it may not disconnect the input figure 10. r-c filter to ride through input shorts c f 10nf r f 100 vs3 ltc4417 g3 vs2 g2 v out v out output 4417 f10 irf7324 m5 m6 irf7324 m3 m4 c l i l + a pplica t ions i n f or m a t ion from the output before the output is dragged below the operating voltage of the ltc4417. the event would cause the ltc4417s internal v ldo supply voltage to collapse. a 100 and 10 nf r-c filter on v out will allow the ltc4417 to ride through such shorts to the input and output, as shown in figure? 10. because v out is also a sense pin for the rev comparator, care should be taken to ensure the voltage drop across the resistor is low enough to not affect the reverse comparators threshold. if the 1 s r-c time constant does not address the issue, increase the capacitance to lengthen the time constant. the initial lag due to the r-c filter on the ltc4417s v out sense and supply pin will cause additional delay in sensing when a reverse condition has cleared, resulting in addi- tional droop when transitioning from a higher voltage to a lower voltage. if the reverse voltage duration is longer than the r-c delay, the voltage differential between the output and the filtered v out , ? v, can be calculated with equation (18). i l is the output load current during the reverse voltage condition and i vout is current into v out , specified in the electrical table. v = i l c l ? c f C i vout ? ? ? ? ? ? ? r f (18) i cc p at h s election tw o separate internal power rails ensure the ltc4417 is functional when one or more input supplies are present and above 2.4 v as well as limit current draw from lower
ltc4417 19 4417f priority back up input supplies. an internal diode-or structure selects the highest voltage input supply as the source for vb ldo . if two supplies are similar in voltage and higher than the remaining input supply, the current will be equally divided between the similar voltage supplies. if all input supplies are equal in voltage, the current is divided evenly between them. to limit current consumption from lower priority backup supplies, the ltc4417 prioritizes the internal v ldo s source supply. the highest priority source is v out , which powers the v ldo when v out is above 2.4 v. if v out is lower than 2.4v, v ldo switches to the highest valid priority input supply, v1, v2 and v3. if no input supply is valid, v ldo is connected to vb ldo , where the diode-or selects high- est input voltage input supply as the source. see typical performance characteristics for more detail. d ual s uppl y o pera tion for instances where only two supplies are prioritized and no features of the third channel are used, ground the v3, ov3, uv3, vs3 and g3 pins of the unused channel. alternatively, the lowest priority ov and uv comparators can be utilized for voltage monitoring when v3 and vs3 are connected to the output and g3 is left open. figure?11 shows an example of the spare ov and uv comparators used to monitor the 5 v output of the ltc3060. valid3 acts as an open drain ov/uv window comparator output. figure 11. dual channel with output voltage monitoring vs1 v1 v out 5v output valid1 valid2 valid3 12v wall adapter c in 2200f 14.4v nicd battery uv1 ov1 r3 806k r2 39.2k r1 60.4k r6 845k r5 26.1k r4 51.1k r9 340k r8 21.5k r7 78.7k r10 1m r11 1m r12 1m v1 invalid v2 invalid 5v output invalid v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 f11 g1 vs2 vs3g2 gnd ltc4417 g3 c v1 0.1f c vs2 1f c vs1 0.1f c v2 0.1f c v3 0.1f + c l 100f v out + + ltc3060 linear regulator irf7324 m3 m4 irf7324 m1 m2 c s 6.8nf r s 2.21k d s bat54
ltc4417 20 4417f a pplica t ions i n f or m a t ion d isabling a ll c hannels with en and shdn driving en below 1 v turns off all external back-to-back p-channel mosfets but does not interrupt input supply monitoring or reset the 256 ms timers. driving en above 1v enables the highest valid priority channel. this feature is essential in cascading applications. for applications where en could be driven below ground, limit the current from en with a 10k resistor. forcing shdn below 0.8 v turns off all external back- to- back p-channel mosfets, disables all ov and uv comparators and resets all 256 ms timers. valid1 , valid2 and valid3 release high to indicate all inputs are invalid, regardless of the input supply condition. the ltc4417 enters into a low current state, consuming only 15 a. when shdn is released or driven above 0.8 v, the ltc4417 is required to revalidate the input supplies before connecting the inputs to v out , as described in the operation section. for applications where shdn could be driven below ground, limit the current from shdn with a 10k resistor. c ascading the ltc4417 can be cascaded to prioritize four or more input supplies. to prioritize four to six supplies, use two ltc4417s with their v out pins connected together and the master ltc4417s cas connected to the slave ltc4417s en as shown in figure 12. the first ltc4417 to validate an input will soft-start the common output. once the output is above 2.4 v, power will be drawn from v out by the other ltc4417 regardless of its input supply conditions. when the master ltc4417 wants to connect one of its input supplies to the v out , it simultaneously initiates a channel turn on and pulls its cas pin low to force the slave ltc4417 to disconnect its channels. a small amount of reverse conduction may occur in this case. the amount of cross conduction will depend on the total turn-on delay of the master channel compared with the turn-off delay of the slave channel. care should be taken to ensure the connection between cas and en is as short as possible, to minimize the capacitance and hence the turn-off delay of the slave channel. when all of the inputs to the master ltc4417 are invalid, the master confirms that all its inputs are disconnected from v out before releasing cas. cas is pulled to the in- ternal v ldo rail with a 20 a current source, allowing the slave ltc4417 to connect its highest valid priority channel to v out . confirmation that all channels are off before the slave is allowed to connect its channel to v out prevents cross conduction from occurring. driving the master ltc4417s en low forces both master and slave to disconnect all channels from the common output and continue monitoring the input supplies. driv- ing the master ltc4417s shdn low places it in to a low current state. while in the low current state, all of its chan- nels are disconnected and cas is pulled high with a 20a current source, allowing the slave ltc4417 to become the figure 12. cascading application vs1 v out en shdn cas g1 ltc4417 master irf7324 m1 m2 disable all channels shdn master v out vs1 v out en shdn cas 4417 f12 g1 ltc4417 slave irf7324 m3 m4 c vs1_2 0.1f c vs1_1 0.1f c l 47f +
ltc4417 21 4417f a pplica t ions i n f or m a t ion master and connect its highest valid priority channel to the common output. if seven, or more, input supplies are prioritized, additional ltc4417s can be added by connect- ing all individual v out pins together and connecting each ltc4417s cas to the next lower priority ltc4417s en. d esign e xample a 2 a multiple input supply system consisting of a 12v supply with a source resistance of 20m, 7.4 v main lithium-ion battery, and a backup 7.4 v lithium-ion battery is designed with priority sourcing from the 12 v supply, as shown in figure 13. power is sourced from the main battery when the 12 v supply is absent and the backup battery is only used when the main battery and 12 v supply are not available. the ambient conditions of the system will be between 25c and 85c. the design limits the output voltage droop to 800mv during switchover. the load capacitor is assumed to have a minimum esr of 50 m at 85 c and 80 m at 25c through paralleling low esr rated aluminum electrolytic capacitors. the input source is allowed to drop 1v. selecting external p-channel mosfet the design starts with selecting a suitable 2 a rated p - channel mosfet with desired r ds( on) . reviewing several mosfet options, the low 18 m r ds(on) , dual p-channel irf7324 with a C20 v bv dss , is chosen for this application. the low 18 m r ds(on) results in a 72 mv combined drop at 25 c and 85 mv drop at 85 c. each p-channel mosfet dissipates 72mw at 25c and 85mw at 85c. inrush current limiting when connecting a higher voltage source to a lower voltage output, significant inrush current can occur. the magnitude of the inrush current can be calculated with equation (19). i inrush = v1C v out(init) r src + esr(c l ) + 2 ? r ds(on) (19) where v out(init) is the v out voltage when initially powered from a supply voltage less than v1, v1 is the higher voltage source, r src is source resistance of v1, esr(c l ) is the esr of the load capacitor, and r ds(on) is the on-resistance of the external back-to-back mosfet. given a total series resistance from input to output, the worst case inrush current will occur when v1 is running 20% high, at 14.4 v, and v out is at its undervoltage limit of 5.6 v. during this condition, a maximum inrush current of 83a will occur, as shown in equation (20). i inrush = 14.4v C 5.6v 20m + 50m + 36m = 83a (20) because the 83 a of inrush current exceeds the 71 a ab- solute maximum pulsed drain current rating, i dm , of the irf7324, inrush current limiting is required. calculating the load capacitance, c l , and inrush current limiting circuitry component, r s , is an iterative process. to start, use equation (14), with 0.79 ? r s ? c s initially set to 10s. to limit the output voltage droop to the desired 800mv, reserve 200 mv for initial droop due to the load current flowing in the esr of the output capacitor. next, choose c l to set the maximum v out droop to 600 mv, as shown in equation (21). c l = 2a ? (3s + 12s + 10s) 600mv c l = 83.3f (21) for margin, choose the initial c l value equal to 100 f and use equation (16) to determine r s . with an allowable 1v input voltage drop and source resistance, r src , of 20m, the input voltage droop of 700 mv is used to set the inrush current of 35 a. the other terms in the equation come from the external p-channel mosfet manufacturers data sheet. the transfer characteristics curve shows the gate voltage, v gs , is approximately 1.8 v when driving the 35a inrush current and the capacitance verses drain-to-source voltage curve shows the maximum c rss is approximately 600pf. c s is set to be greater than ten times c rss , or 6.8nf. to ensure the designed inrush current is lower than the absolute maximum pulse drain current rating, i dm , calculate r s using the maximum value for ?v g(sink) and c l , and the minimum value for c s . for aluminum
ltc4417 22 4417f a pplica t ions i n f or m a t ion figure 13. industrial hand held computer electrolytic capacitors, add 20% to c l and for ceramic np0 c s capacitors subtract 5%. r s = (6v C 1.8v) ? 120f ? 20m 6.5nf ? 700mv r s = 2.22k (22) the standard value of 2.21 k is chosen for r s and c vs1 is chosen to be ten times c s or 68nf. although 1.8v is a typical value for v gs , there is sufficient margin C even if v gs = 0v, the resulting i dm is lower than the 71a rating. with r s and c s known, the desired load capacitance with inrush current limiting is checked with equation? (14) as shown in equation (23). because the required load capacitance of 90 f is lower than the chosen load ca- pacitor of 100f , the initial choice of 100 f is suitable. c l 2a ? (3s + 12s + 0.79 ? 2.21k ? 6.8nf) 600mv c l 90f (23) vs1 v1 v out valid1 valid2 valid3 12v supply c in 2700f 7.4v li-ion battery (2 3.7v) uv1 ov1 r3 806k r2 41.2k r1 60.4k r6 768k r5 53.6k r4 113k r9 768k r8 53.6k r7 113k r10 1m r11 1m r12 1m v2 invalid v3 invalid v1 invalid r hys 255k 1% v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 f13 g1 vs2 vs3 g2 c vs3 0.1f gnd ltc4417 g3 irf7324 m5 m6 irf7324 m3 m4 irf7324 m1 m2 c vs2 0.1f c vs1 68nf c v1 0.1f c v2 0.1f c v3 0.1f + c l 100f v out + + 7.4v li-ion battery (2 3.7v) + r s 2.21k d s bat54 c s 6.8nf 140k 140k
ltc4417 23 4417f a pplica t ions i n f or m a t ion significant power is dissipated during the channel transi- tion time. the soa of the p-channel mosfet should be checked to make sure their soa is not violated. worst case slew rate limited channel transition time would occur when the lithium-ion batteries are running low at 5.6 v, and the supply connects while running 20% high, at 14.4 v. this results in a time of 25 s, as shown in equation (24). dt = (14.4v C 5.6v) ? 100f 35a dt = 25s (24) the irf7324 thermal response curve at 25 s shows z ja to be approximately 0.18 for a single pulse. the z ja of 0.18 results in a maximum transient power dissipation of 694w at 25 c and 361 w at 85 c. the external p-channel mosfets will dissipate no more than 8.8v ? 37 a = 325w during this period, below the available 361w at 85c. the initial soft-start period will also force the external back-to-back mosfets to dissipate significant power. to check the soa during this period, start with equation (9). t startup (ms) = 12v 5[ v/ms] t startup (ms) = 2.4ms (25) i maxcap current of 500 ma is calculated using equation (10). i maxcap = 100f ? 5[v/ms] i maxcap = 500ma (26) the worst case soft-start power dissipation from equa- tion (11) is: p ss (w) = 12v ? 500ma p ss (w) = 6w (27) the soft-start power dissipation of 6 w is well below the calculated transient power dissipation (p dm ) of 79.4 w at a t c of 25 c. an ambient temperature, t a , of 85 c results in a p dm of 41.3 w, indicating it is sufficient to handle the 2.4ms transient 6 w power dissipation. a graphical check with the manufacturers soa curves confirms sufficient operating margin. setting operational range assuming the 12 v source has a tolerance of 20%, the input source has an operational undervoltage limit of 9.6v and an overvoltage limit of 14.4 v. ideally the uv1, uv2 and uv3 and ov1, ov2 and ov3 thresholds would be set to these limits. however, since the actual threshold varies by 1.5% and resistor tolerances are 1%, ov and uv limits must be adjusted to 26% or 8.9 v and 15.1v. further, instead of using the internal fixed 30 mv, a uv hysteresis of 200 mv is set using an external hysteresis current of 250na. the d esign p rocess starts with setting r hys using equation (1). r hys = 63mv 250na = 252k (28) the nearest standard value is 255k. now set the uv hysteresis value using r3 r3 = desired hysteresis i ovuv(hys) = 200mv 247na = 810k (29) the nearest standard value is 806k. with r3 set, the remaining resistance can be determined with r1,2 = r3 uv th(falling) C v ovuv(thr) = 806k 8.9v C 1v = 102k (30) r1 is r1 = r1,2 + r3 ov th(rising) = 102k + 806k 15.1v = 60.1k (31) the nearest 1% standard value is: 60.4k. r2 is r2 = r1,2 C r3 = 102k C 60.4k = 41.6k (32) the nearest 1% standard value is 41.2k.
ltc4417 24 4417f a pplica t ions i n f or m a t ion because this is a single resistive string r2, r3, and i ov_uv(hys) sets the hysteresis voltage with equation (30) ov hys = (r2 + r3) ? i ovuv(hys) = (41.2 k + 806k) ? 247na = 209mv (33) this results in an ov threshold of 15.0 v and uv threshold of 8.9 v. with hysteresis, the ov hys threshold is 14.8v and the uv hys threshold is 9.1 v. for the desired ov and uv 6% accuracy, 1% resistors used in this example are acceptable. values for r4 to r6 and r7 to r9 for v2 and v3 are similarly calculated. layout considerations sheet resistance of 1 oz copper is ~530? per square. although small, resistances add up quickly in high current applications. keep high current traces short with minimum trace widths of 0.02 " per amp to ensure traces stay at a reasonable temperatures. using 0.03 " per amp or wider is recommended. to improve noise immunity, place ov/ uv resistive dividers as close to the ltc4417 as possible. transient voltage suppressors should be located as close to the input connector as possible with short wide traces to gnd. figure 14 shows a partial layout that addresses these issues. figure 14. recommended pcb layout 1 2 3 4 5 6 7 8 9 10 11 12 to v3 common source to v3 common gate transient voltage suppressor gnd gnd 24 23 22 21 20 19 18 17 16 15 14 13 from v1 input source 0.03" per ampere not to scale en shdn hys uv1 ov1 uv2 ov2 uv3 ov3 valid1 valid2 valid3 v1 v2 v3 vs1 g1 vs2 g2 vs3 g3 v out cas gnd r3 r2 r1 r6 r5 r4 c v1 g c v2 c v3 r9 r8 r7 from v2 input source to v3 input supply g s s g g s s d d d to output d
ltc4417 25 4417f typical a pplica t ions vs1 v1 v out valid1 valid2 valid3 12v wall adapter c in1 2200f 12v nicd battery uv1 ov1 r3 1.02m r2 48.7k r1 76.8k r6 1.02m r5 36.5k r4 76.8k r9 1.0m r8 40.2k r7 90.9k r10 1m r11 1m r12 1m v2 invalid v3 invalid v1 invalid r hys 316k v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 ta02 g1 vs2 vs3 g2 c vs3 0.1f gnd ltc4417 g3 irf7324 m5 m6 irf7324 m3 m4 irf7324 m1 m2 c vs2 1f c vs1 0.1f c v1 0.1f c v2 0.1f c v3 0.1f + c l 100f v out + + 11.1v li-ion battery (3 3.7v) + r s 2.21k d s bat54 c s 6.8nf 12v system using swappable and backup batteries
ltc4417 26 4417f typical a pplica t ions 18v system with reverse voltage protection vs1 v1 v out valid1 valid2 valid3 18v wall adapter 11.1v li-ion battery d4 smbj26a uv1 ov1 r3 1.02m r2 11.8k r1 54.9k r6 768k r5 90.9k r4 75k r9 698k r8 16.9k r7 49.9k v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 ta03 g1 vs2 vs3 g2 gnd ltc4417 g3 v out fds4685 fds4685 m5 m6 fds4685 fds4685 m3 m4 fds4685 fds4685 m1 m2 + 12v lead-acid battery + d1 smbj26ca d2 smbj26ca d3 smbj26ca c vs3 0.1f c vs2 0.1f c vs1 0.1f c in1 2200f c v1 0.1f c v2 0.1f c v3 0.1f c l 100f
ltc4417 27 4417f typical a pplica t ions 28v transient hold-up supply for solid state drives (ssd) vs1 v1 v out valid1 valid2 valid3 12v system supply c v2 35v tantalum uv1 ov1 r3 806k r10 1m invalid 12v system ltc3851-1.5v/15a buck please refer to the ltc3851 data sheet for specific application information invalid supercap supercap not fully charged r2 15.8k r1 66.5k r6 806k r5 127k r4 33.2k r8 1.02m r7 41.2k r9 124k v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 ta04 g1 vs2 vs3g2 gnd ltc4417 g3 v out fds4685 fds4685 m3 m4 fds4685 fds4685 m1 m2 c l 100f pgo0d run tk/ss i th freq/pllfltr v in tg sw pllin/mode bg sense + sense ? v fb gnd c16 0.22f c4 0.1f r17 10k ltc3851 5v, 15a output l2 0.68h c9 0.1f c vs2 0.1f c vs1 1f c1 2200pf c17 0.1f c5 4.7f boost r13 100k r15 255k r19 13k r16 48.7k r20 82.5k r14 15k r18 100k d1 cmdsh2-3 intv cc d2 mbrs360 c2 330f 2 d3 mbrs340 q2 std30nfl06l m5 q1 std30nfl06l c15 47pf lt3956 supercap charger with input current limit please refer to the lt3956 data sheet for specific application information r12 1m r11 1m + lt3956 gnd v c intv cc en/uvlo v ref v in r23 1 c7 4.7f c8 10nf c10 10f sw fb vmode pwm l1a 33h ctrl r27 30.1k r32 1m isp isn pwmout ss r24 28.7k rt r29 40.2k r30 1m r28 2k r21 536k r22 25k r31 59k r26 10k r25 14k q3 bc817-25 l1b 33h c11 10f c3 330pf r s 1.43k d s bat54 c s 6.8nf c v1 470f +
ltc4417 28 4417f typical a pplica t ions selecting from usb, firewire, and li-ion battery power sources vs1 v1 v out valid1 valid2 valid3 4.35v to 5.25v usb c in1 10f 8v to 30v firewire ieee1394 uv1 ov1 r3 309k r10 1m usb invalid firewire invalid li_ion invalid r11 1m r12 1m r2 24.9k r1 75k r6 576k r5 78.7k r4 20.5k r9 931k r8 63.4k r7 137k v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 ta05 g1 vs2 vs3 g2 gnd ltc4417 g3 v out fds4685 fds4685 m5 m6 fds4685 fds4685 m3 m4 fds4685 fds4685 m1 m2 7.4v li-ion battery + c in2 22f c l 47f c vs3 0.1f c vs2 1f c vs1 0.1f r s 1k d s bat54 c s 6.8nf c v3 0.1f c v2 0.1f c v1 0.1f
ltc4417 29 4417f typical a pplica t ions wall adapter and usb input with battery backup vs1 v1 v out valid1 valid2 valid3 5v wall adapter 4.35v to 5.25v usb uv1 ov1 r3 412k r13 1m r12 1m r14 1m r2 37.4k r1 95.3k r4 412k r5 33.2k r6 100k r9 432k r8 80.6k r7 86.6k r11 562k v2 uv2 ov2 r10 52.3k r hys 249k v3 en shdn hys cas uv3 ov3 4417 ta06 g1 vs2 vs3 g2 gnd ltc4417 g3 v out si4931dy m5 m6 si4931dy m3 m4 si4931dy m1 m2 4 aa battery + c in2 10f c vs3 0.1f c vs2 0.1f c vs1 0.1f c v3 0.1f c v2 0.1f wall adapter invalid usb invalid 4 aa battery invalid c l 47f + c in1 1000f + c v1 0.1f
ltc4417 30 4417f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .337 ? .344* (8.560 ? 8.738) gn24 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 161718192021222324 15 14 13 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b)
ltc4417 31 4417f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b)
ltc4417 32 4417f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1112 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments LTC4411 2.6a low loss ideal diode in thinsot? internal 2.6a p-channel, 2.6v to 5.5v, 40a i q , sot-23 package ltc4412hv 36v low loss powerpath controller in thinsot 2.5v to 36v, p-channel, 11a i q , sot-23 package ltc4415 dual 4a ideal diodes with adjustable current limit dual internal p-channel, 1.7v to 5.5v, msop-16 and dfn-16 packages ltc4416 36v low loss dual powerpath controller for large pfets 3.6v to 36v, 35a i q per supply, msop-10 package ltc4355 positive high voltage ideal diode-or with supply and fuse monitors dual n-channel, 9v to 80v, so-16, msop-16 and dfn-14 packages ltc4359 ideal diode controller with reverse input protection n-channel, 4v to 80v, msop-8 and dfn-6 packages ltc2952 pushbutton powerpath controller with supervisor 2.7v to 28v, on/off timers, 8kv hbm esd, tssop-20 and qfn-20 packages dual channel ltc4417 application with output voltage monitoring using third channel 10f vs1 v1 v out 5v output valid1 valid2 valid3 12v wall adapter c in 2200f 14.4v nicd battery uv1 ov1 r3 806k r2 39.2k r1 60.4k r6 845k r5 26.1k r4 51.1k r9 357k r8 15.4k r7 84.5k r10 1m r11 1m r12 1m v1 invalid v2 invalid 5v output invalid v2 uv2 ov2 v3 en shdn hys cas uv3 ov3 4417 ta07 g1 vs2 vs3g2 gnd ltc4417 g3 irf7324 m3 m4 irf7324 m1 m2 c v1 0.1f c vs2 1f c1 10nf c vs1 0.1f c v2 0.1f c v3 0.1f + c l 100f v out + + in out ref/byp c2 10nf adj gnd shdn lt3060-5 r s 2.21k d s bat54 c s 6.8nf

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